ADC SNR Limited by Clock Jitter

Formula

Description

Sample-clock jitter sets a hard ceiling on the signal-to-noise ratio of a high-speed ADC, independent of its resolution. Because the error from sampling at the wrong instant grows with the input slew rate, the jitter-limited SNR falls as the input frequency rises. For fast inputs this term, not quantization, dominates—so a low-jitter clock is essential for high-resolution high-frequency digitising.

Variables

• SNR — Jitter-limited signal-to-noise ratio (dB)
• f — Analog input frequency (Hz)
• tj — RMS aperture/clock jitter (s)

Practical Notes

This SNR combines (root-sum-square) with the quantization and thermal-noise limits; the smallest dominates. To digitise a 70 MHz IF at 12-bit SNR you need roughly 1 ps or better clock jitter.