ADC SNR Limited by Clock Jitter

SNR = −20 · log10(2π · f · tj)

Quick answer

This calculator solves SNR = −20 × log10(2π × f × tj) for SNR. With Input Frequency 10 MHz, RMS Jitter 100 ps, the result is 44.04 dB. It solves in 3 directions, so you can enter the values you have and get the one you need.

Calculator

SNR (dB)
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Formula

SNR = −20 × log10(2π × f × tj)

Description

Sample-clock jitter sets a hard ceiling on the signal-to-noise ratio of a high-speed ADC, independent of its resolution. Because the error from sampling at the wrong instant grows with the input slew rate, the jitter-limited SNR falls as the input frequency rises. For fast inputs this term, not quantization, dominates—so a low-jitter clock is essential for high-resolution high-frequency digitising.

Variables

  • SNR — Jitter-limited signal-to-noise ratio (dB)
  • f — Analog input frequency (Hz)
  • tj — RMS aperture/clock jitter (s)

Practical Notes

This SNR combines (root-sum-square) with the quantization and thermal-noise limits; the smallest dominates. To digitise a 70 MHz IF at 12-bit SNR you need roughly 1 ps or better clock jitter.

Symbols and units

Symbol Meaning Default unit Accepted units
SNR SNR dB dB
f Input Frequency MHz Hz, kHz, MHz, GHz
tj RMS Jitter ps ps, ns, µs, ms, s, min, h

Step by step

  1. 1. What you know: Input Frequency 10 MHz, RMS Jitter 100 ps
  2. 2. The relation: SNR = −20 × log10(2π × f × tj)
  3. 3. Substitute: f = 10 MHz, tj = 100 ps
  4. 4. Result: SNR = 44.04 dB

Worked examples

Minimum range

Given: Input Frequency 100 kHz, RMS Jitter 1 ps

Result: SNR = 124 dB

Low range

Given: Input Frequency 1 MHz, RMS Jitter 10 ps

Result: SNR = 84.04 dB

Typical

Given: Input Frequency 10 MHz, RMS Jitter 100 ps

Result: SNR = 44.04 dB

High range

Given: Input Frequency 100 MHz, RMS Jitter 0.5 ns

Result: SNR = 10.06 dB

Maximum range

Given: Input Frequency 1 GHz, RMS Jitter 5 ns

Result: SNR = -29.94 dB

Solving for each variable

Solve for SNR

Input Frequency 100 kHz, RMS Jitter 1 ps → 124 dB

Solve for Input Frequency

SNR 0.3 dB, RMS Jitter 1 ps → 153.8 GHz

Solve for RMS Jitter

SNR 0.3 dB, Input Frequency 100 kHz → 1.538 µs

How SNR changes with Input Frequency

Input Frequency (input) SNR (result)
1 MHz 64.04 dB
2.5 MHz 56.08 dB
5 MHz 50.06 dB
7.5 MHz 46.54 dB
10 MHz 44.04 dB
15 MHz 40.51 dB
20 MHz 38.02 dB
40 MHz 32 dB
70 MHz 27.13 dB
100 MHz 24.04 dB

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Frequently asked questions

How do you calculate ADC SNR Limited by Clock Jitter?

Use SNR = −20 × log10(2π × f × tj). With Input Frequency 10 MHz, RMS Jitter 100 ps, SNR works out to 44.04 dB.

What is the formula for ADC SNR Limited by Clock Jitter?

The formula is SNR = −20 × log10(2π × f × tj). Sample-clock jitter sets a hard ceiling on the signal-to-noise ratio of a high-speed ADC, independent of its resolution.

How do you find Input Frequency when you know the other values?

Rearrange for Input Frequency: with SNR 0.3 dB, RMS Jitter 1 ps, Input Frequency is 153.8 GHz.

How do you find RMS Jitter when you know the other values?

Rearrange for RMS Jitter: with SNR 0.3 dB, Input Frequency 100 kHz, RMS Jitter is 1.538 µs.

Related Concepts

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