Digital Logic Formulas
Digital logic formulas quantify logic thresholds, drive strength, and timing margins between gates. These calculators help you verify interfaces and budget propagation delays. They are essential for reliable high-speed and mixed-voltage design.
Digital Logic Formula Calculators
- CMOS Dynamic Power P = C × V² × f Load Capacitance 1 pF, Supply Voltage 0.33 V, Switching Frequency 100 kHz → Power = 0.01089 µW
- Rise Time to Bandwidth BW = 0.35 / tr Rise Time 100 ps → Bandwidth = 3.5 GHz
- Setup Time Margin Tmargin = Tclk − Tpd − Tsetup Clock Period 0.22 ns, Propagation Delay 0.47 ns, Setup Time 47 ps → Timing Margin = -0.297 ns
- Static Power Dissipation P = Vdd × Ileakage Supply Voltage 0.33 V, Leakage Current 100 nA → Static Power = 0.033 µW
- Clock Skew Timing Margin Tmargin = Tclk − Tskew − Tsetup Clock Period 0.22 ns, Clock Skew 0.47 ns, Setup Time 47 ps → Timing Margin = -0.297 ns
- Logic Noise Margin NMH = VOH_min − VIH_min Output High (min) 0.726 V, Input High (min) 1.55 V → Noise Margin = -0.824 V
- Digital Fanout N = Isource / Isink_per_gate Driver Source Current 100 µA, Sink Current per Gate 0.22 mA → Maximum Fanout = 0.4545
- Pull-Up Resistor for Logic R = (Vcc − VOH) / Isink Supply Voltage 0.33 V, Max Low-Side Voltage 0.726 V, Sink Current 100 µA → Pull-Up Resistor = -3.96 kΩ
- Resistive Level Shifter Ratio R1/R2 = (Vin − Vout) / Vout Input (Higher) Voltage 0.33 V, Output (Lower) Voltage 0.726 V → R1/R2 Ratio = -0.5455
- Number of States (n bits) States = 2ⁿ Number of Bits 0.055 → Number of States = 1.039
- Counter Frequency Division fout = fin / 2ⁿ Input Frequency 100 kHz, Counter Stages 0.025 → Output Frequency = 98.28 kHz
Worked result for every Digital Logic formula
| Formula | Expression | Worked result |
|---|---|---|
| CMOS Dynamic Power | P = C × V² × f | Load Capacitance 1 pF, Supply Voltage 0.33 V, Switching Frequency 100 kHz → Power = 0.01089 µW |
| Rise Time to Bandwidth | BW = 0.35 / tr | Rise Time 100 ps → Bandwidth = 3.5 GHz |
| Setup Time Margin | Tmargin = Tclk − Tpd − Tsetup | Clock Period 0.22 ns, Propagation Delay 0.47 ns, Setup Time 47 ps → Timing Margin = -0.297 ns |
| Static Power Dissipation | P = Vdd × Ileakage | Supply Voltage 0.33 V, Leakage Current 100 nA → Static Power = 0.033 µW |
| Clock Skew Timing Margin | Tmargin = Tclk − Tskew − Tsetup | Clock Period 0.22 ns, Clock Skew 0.47 ns, Setup Time 47 ps → Timing Margin = -0.297 ns |
| Logic Noise Margin | NMH = VOH_min − VIH_min | Output High (min) 0.726 V, Input High (min) 1.55 V → Noise Margin = -0.824 V |
| Digital Fanout | N = Isource / Isink_per_gate | Driver Source Current 100 µA, Sink Current per Gate 0.22 mA → Maximum Fanout = 0.4545 |
| Pull-Up Resistor for Logic | R = (Vcc − VOH) / Isink | Supply Voltage 0.33 V, Max Low-Side Voltage 0.726 V, Sink Current 100 µA → Pull-Up Resistor = -3.96 kΩ |
| Resistive Level Shifter Ratio | R1/R2 = (Vin − Vout) / Vout | Input (Higher) Voltage 0.33 V, Output (Lower) Voltage 0.726 V → R1/R2 Ratio = -0.5455 |
| Number of States (n bits) | States = 2ⁿ | Number of Bits 0.055 → Number of States = 1.039 |
| Counter Frequency Division | fout = fin / 2ⁿ | Input Frequency 100 kHz, Counter Stages 0.025 → Output Frequency = 98.28 kHz |
Variables used across Digital Logic formulas
- P — Dynamic power dissipation (W)
- C — Total switched capacitance (F)
- V — Supply voltage (V)
- f — Switching frequency (Hz)
- BW — Approximate bandwidth containing significant spectral content (Hz)
- tr — Signal rise time, 10% to 90% (s)
- Tmargin — Available timing slack (s)
- Tclk — Clock period (s)
- Tpd — Total propagation delay through logic and routing (s)
- Tsetup — Flip-flop setup time requirement (s)
- Vdd — Supply voltage (V)
- Ileakage — Total leakage current (A)
- Tskew — Clock skew between source and destination (s)
- NM — Noise margin voltage (V)
- V_OH — Minimum output high voltage (V)
- V_IH — Minimum input high voltage threshold (V)
- N — Maximum number of gates that can be driven
- I_source — Maximum current the driver can source/sink (A)
- I_sink — Input current required by each receiving gate (A)
- R — Pull-up resistor value (Ω)
- V_cc — Supply voltage (V)
- V_OL — Maximum acceptable low output voltage (V)
- R₁/R₂ — Ratio of upper to lower resistor
- V_in — Input logic high voltage (V)
- V_out — Desired output logic high voltage (V)
- States — Number of distinct values (codes)
- n — Number of bits
- fout — Divided output frequency (Hz)
- fin — Input clock frequency (Hz)
Questions people ask about Digital Logic
- Bw time rise — Rise Time to Bandwidth
- Number of n states — Number of States (n bits)
Related Formula Categories
Browse the full formulas index for all 32 categories.