Digital Logic Formulas
Digital logic formulas quantify logic thresholds, drive strength, and timing margins between gates. These calculators help you verify interfaces and budget propagation delays. They are essential for reliable high-speed and mixed-voltage design.
Digital Logic Formula Calculators
- CMOS Dynamic Power P = C × V² × f
- Rise Time to Bandwidth BW = 0.35 / tr
- Setup Time Margin Tmargin = Tclk − Tpd − Tsetup
- Static Power Dissipation P = Vdd × Ileakage
- Clock Skew Timing Margin Tmargin = Tclk − Tskew − Tsetup
- Logic Noise Margin NMH = VOH_min − VIH_min
- Digital Fanout N = Isource / Isink_per_gate
- Pull-Up Resistor for Logic R = (Vcc − VOH) / Isink
- Resistive Level Shifter Ratio R1/R2 = (Vin − Vout) / Vout
- Number of States (n bits) States = 2ⁿ
- Counter Frequency Division fout = fin / 2ⁿ
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