Counter Frequency Division

Formula

Description

A binary ripple counter divides an input clock frequency by two at each stage, so an n-stage counter divides by 2 to the n. This is the standard way to derive slow clocks from a fast oscillator—generating real-time-clock ticks, baud-rate references, or PWM timebases. The final output is a square wave at the divided frequency.

Variables

• fout — Divided output frequency (Hz)
• fin — Input clock frequency (Hz)
• n — Number of flip-flop (divide-by-2) stages

Practical Notes

For a non-power-of-two divisor use a modulo-N (programmable) counter. Each stage also halves duty-cycle jitter accumulation but adds ripple-propagation delay in asynchronous counters.